MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 149

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.4.2.2
Once POR for both the device and the VDDPLL supplies have negated, the PLL will begin its lock
detect algorithm. However, if a valid reference is not present, the PLL will continue to operate in
SCM until one is present. The system will not come out of reset until a valid reference is present
and the PLL has acquired lock at the default MFD (see
Following the initial lock with the default MFD, the MFD in the SYNCR may be modified for the
desired operating frequency. If the PLL is not able to lock due to an MFD and crystal frequency
combination that attempts to force the current controlled oscillator (ICO) outside of its operating
range, reset will not negate.
Refer to
7.4.3
In normal PLL clock mode, the default core frequency is one and a half times (1.5x) the reference
frequency after reset. The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency
multiplier with default values of RFD = 0b010 (÷4) and MFD = 0b001 (×6) (see
When programming the PLL, do not exceed the maximum system clock frequency listed in the
electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs
when the MFD bits are changed. If frequency modulation is going to be enabled, the maximum
allowable frequency must be reduced by the programmed ∆F
Freescale Semiconductor
1. Determine the appropriate value for the MFD and RFD fields in the SYNCR; remember to
2. Write a value of RFD factor (from step 1) + 1 to the RFD field of the SYNCR.
3. If frequency modulation is enabled (by writing to the EXP bit field), disable frequency
4. If programming the MFD, write the MFD value from step 1 to the SYNCR. If enabling
include the ∆F
clocks can be minimized by selecting the maximum MFD factor that can be paired with an
RFD factor to provide the required frequency. See
modulation by writing 0x0 to the DEPTH field of the SYNCR.
frequency modulation, skip this step.
Section 10.4.1.1, “Power-On
System Clock Generation
External Reset
When running in an unlocked state, the clocks generated by the PLL
are not guaranteed to be stable and may exceed the maximum
specified frequency of the device. It is always recommended that the
RFD be used as described in
Generation,”
overshoot of the PLL clocks.
m
if frequency modulation is enabled. The amount of jitter in the system
to insulate the system from any potential frequency
MCF5271 Reference Manual, Rev. 2
Reset,” for more information.
NOTE
Section 7.4.3, “System Clock
Table 7-5
Table
m
.
7-5.
for the default MFD value).
Functional Description
Table
7-5).
7-15