MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 246

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
General Purpose I/O Module
12.3.1.7.4 QSPI Drive Strength Control Register (DSCR_QSPI)
The DSCR_QSPI register controls the output drive strengths of the following pins: QSPI_CS1,
QSPI_CS0, QSPI_SCK, QSPI_DIN, and QSPI_DOUT.
12.3.1.7.5 Timer Drive Strength Control Register (DSCR_TIMER)
The DSCR_TIMER register controls the output drive strengths of the following pins: DT3IN,
DT3OUT, DT2IN, DT2OUT, DT1IN, DT1OUT, DT0IN, and DT0OUT.
12-30
Bits
7–1
Bits
0
1
0
Figure 12-42. QSPI Drive Strength Control Register (DSCR_QSPI)
DSCR_QSPI QSPI drive strength. This bit sets the drive strength on the QSPI_CS1, QSPI_CS0,
DSCR_
UART0
Name
Address
Name
Table 12-20. DSCR_UART Field Descriptions (Continued)
Reset
W
R
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Table 12-21. DSCR_QSPI Field Descriptions
Reserved, should be cleared.
UART0 drive strength. This bit sets the drive strength on the U0RXD, U0TXD, U0CTS, and
U0RTS pins.
0 U0RXD, U0TXD, U0CTS, and U0RTS pins set at low drive
1 U0RXD, U0TXD, U0CTS, and U0RTS pins set at high drive
Reserved, should be cleared.
QSPI_SCK, QSPI_DIN, and QSPI_DOUT pins.
0 Pins set at low drive
1 Pins set at high drive
0
0
7
0
0
6
MCF5271 Reference Manual, Rev. 2
0
0
5
IPSBAR + 0x10_0054
0
0
4
Description
0
0
3
Description
2
0
0
1
0
0
See Note
DSCR_
QSPI
0
Freescale Semiconductor

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