MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 219
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.1.1 Overview
The MCF5271 ports module controls the configuration for various external pins, including those
used for:
12.1.2 Features
The MCF5271 ports includes these distinctive features:
12.2
The MCF5271 ports control the functionality of several external pins. These pins are listed in
Table 12-2
After reset ports ADDR, DATAH, DATAL, BUSCTL, BS and CS are configured for external
memory. They are available for the user as GPIO if the corresponding registers are set
appropriately. All other ports default to GPIO after reset.
Freescale Semiconductor
• External bus accesses
• External device selection
• Ethernet data and control
• I
• QSPI
• 32-bit platform timers
• Control of primary function use
• General purpose I/O support for all ports
— On all supported GPIO ports
— On pins whose GPIO (or lack thereof) is not supported by MCF5271 ports module:
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
2
C serial control
IRQ[7:1]
External Signal Description
under the GPIO column.
In this table and throughout this document a single signal within a
group is designated without square brackets (i.e., A24), while
designations for multiple signals within a group use brackets (i.e.,
A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
MCF5271 Reference Manual, Rev. 2
NOTE
External Signal Description
12-3
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