MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 275

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
27–25
21–20
24-23
Bits
29
28
22
19
SSIZE
Name
DINC
BWC
SINC
CS
AA
—
Table 14-4. DCRn Field Descriptions (Continued)
Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting
Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that
is, transfers are optimized based on the address and size. See
“Auto-Alignment.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned;
Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count
reaches a multiple of the BWC value, the DMA releases the bus.
Reserved, should be cleared.
Source increment. Controls whether a source address increments after each successful
transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
Source size. Determines the data size of the source bus cycle for the DMA control module.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
Destination increment. Controls whether a destination address increments after each
successful transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
the START bit, or external by asserting DREQn.
otherwise, destination accesses are auto-aligned. Source alignment takes precedence
over destination alignment. If auto-alignment is enabled, the appropriate address
register increments, regardless of DINC or SINC.
MCF5271 Reference Manual, Rev. 2
BWC
000
001
010
100
101
011
110
111
Description
DMA has priority and does not negate
its request until transfer completes.
Number of kilobytes per block
1024 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
Section 14.4.4.2,
Memory Map/Register Definition
14-11