MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 347

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into
transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register.
User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows
from the transmit FIFO into the transmit block and receive data flows from the receive block into
the receive FIFO.
The user controls the FEC by writing, through the SIF (Slave Interface) module, into control
registers located in each block. The CSR (control and status register) block provides global control
(e.g. Ethernet reset and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external
physical layer device (transceiver). This serial channel consists of the EMDC (Management Data
Clock) and EMDIO (Management Data Input/Output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive
data and receive descriptor accesses to run independently.
The Transmit and Receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The Message Information Block (MIB) maintains counters for a variety of network events and
statistics. It is not necessary for operation of the FEC but provides valuable counters for network
management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and
some of the IEEE 802.3 counters. See
more information.
19.1.3 Features
The FEC incorporates the following features:
Freescale Semiconductor
• Support for three different Ethernet physical interfaces:
• IEEE 802.3 full duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
DMA references in this section refer to the FEC’s DMA engine. This
DMA engine is for the transfer of FEC data only, and is not related to
the DMA controller described in
Module,” nor to the DMA timers described in
Timers
(DTIM0–DTIM3).”
MCF5271 Reference Manual, Rev. 2
Section 19.2.3, “MIB Block Counters Memory
NOTE
Chapter 14, “DMA Controller
Chapter 22, “DMA
Map” for
Introduction
19-3