MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 81

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.7.7
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated
by the attempted execution of an undefined line-A opcode.
3.7.8
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated
by attempted execution of an undefined line-F opcode.
3.7.9
This special type of program interrupt is discussed in detail in
exception is generated in response to a hardware breakpoint register trigger. The processor does
not generate an IACK cycle but rather calculates the vector number internally (vector number 12).
3.7.10 RTE and Format Error Exception
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate
the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal
to {4,5,6,7} generates a format error. The exception stack frame for the format error is created
without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from
M68000 applications. On M68000 family processors, the SR was located at the top of the stack.
On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero.
Thus, if an RTE is attempted using this “old” format, it generates a format error on a ColdFire
processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the
second longword operand, (3) adjusts the stack pointer by adding the format value to the
auto-incremented address after the fetch of the first longword, and then (4) transfers control to the
instruction address defined by the second longword operand within the stack frame.
3.7.11 TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful for
implementing system calls.
3.7.12 Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate
vector from the interrupt controller using an IACK cycle. See
Modules,”
Freescale Semiconductor
Unimplemented Line-A Opcode
Unimplemented Line-F Opcode
Debug Interrupt
for details on the interrupt controller.
MCF5271 Reference Manual, Rev. 2
Chapter 32, “Debug Support.”
Chapter 13, “Interrupt Controller
Processor Exceptions
This
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