MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 337

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Memory Map/Register Definition
18.3.5.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and SD_SCAS
latency, through the SDRAM component’s mode register. SD_SCAS latency is a function of the
speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates
at a SD_SCAS latency of 1, 2, or 3.
Although the MCF5271 DRAM controller supports bursting operations, it does not use the
bursting features of the SDRAMs. Because the MCF5271 can burst operand sizes of 1, 2, 4, or 16
bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic.
Therefore, the MCF5271 DRAM controller generates the burst cycles rather than the SDRAM
device. Because the MCF5271 generates a new address and a
or
command for each
READ
WRITE
transfer within the burst, the SDRAM mode register should be set either not to burst or to a burst
length of one. This allows bursting to be controlled by the MCF5271.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the
base address and mask registers must be set to the appropriate configuration to allow the mode
register to be set. Note that improperly set DMR mask bits may prevent access to the mode register
address. Thus, the user should determine the mapping of the mode register address to the
MCF5271 address bits to find out if an access is blocked. If the DMR setting prohibits mode
register access, the DMR should be reconfigured to enable the access and then set to its necessary
configuration after the
command executes.
MRS
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to
the SDRAM address space generates the
command to that SDRAM. The address of the access
MRS
should be selected to place the correct mode information on the SDRAM address pins. The address
is not multiplexed for the
command. The
access can be a read or write. The important
MRS
MRS
thing is that the address output of that access needs the correct mode programming information on
the correct address bits.
Figure 18-10
shows the
command, which occurs in the first clock of the bus cycle.
MRS
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
18-19