MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 178

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Configuration Module (CCM)
9.1.3
The MCF5271 device only operates in master mode. In master mode, the central processor unit
(CPU) can access external memories and peripherals.The external bus consists of a 32-bit data bus
and 24 address lines. The available bus control signals include R/W, TS, TIP, TSIZ[1:0], TA, TEA,
OE, and BS[3:0]. Up to eight chip selects can be programmed to select and control external
devices and to provide bus cycle termination. When interfacing to 16-bit ports, the port DATAL
and DATAH (D[15:0]) pins and BS[1:0] can be configured as general-purpose input/output (I/O).
9.2
Table 9-1
9.2.1
If the external RCON pin is asserted during reset, then various chip functions, including the reset
configuration pin functions after reset, are configured according to the levels driven onto the
external data pins (see
are driven to reflect the levels on the external configuration pins to allow for module configuration.
9.2.2
The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. Refer to
Chapter 7, “Clock Module”
9-2
• Selects low-power configuration
• Selects transfer size function of the external bus
• Selects processor status (PSTAT) and processor debug data (DDATA) functions
• Selects BDM or JTAG mode
provides an overview of the CCM signals.
Modes of Operation
External Signal Descriptions
RCON
CLKMOD[1:0]
1
RCON
CLKMOD[1:0]
D[25:24, 21:19, 16]
Refer to
Name
Chapter 7, “Clock Module”
Section 9.4, “Functional
for more information.
Reset configuration select
Clock mode select
Reset configuration override pins
Table 9-1. Signal Properties
MCF5271 Reference Manual, Rev. 2
Function
for more information.
1
Description”). The internal configuration signals
Internal weak pull-up device
Reset State
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