MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 509
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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26.4.2.3 HMAC Hash
26.4.3
EHMAC can only be performed with the SHA-1 algorithm. The Enhanced HMAC requires the
keys to be hashed with IPAD and OPAD prior to the step below. The IPAD and OPAD step can be
Freescale Semiconductor
10. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest and the
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, and HMAC.
4. MDMDS register write. Load this register with the length of the message from the OPAD
5. Direct context load of (OPAD XOR key) into MDx1 registers from the OPAD step in the
6. Direct context load of (IPAD XOR key) into MDx0 registers from the IPAD step.
7. Direct context load of MDMDS register from the IPAD step (this should be 64 bytes).
8. Fill data FIFO with message to be hashed.
9. MDDSR register write. Load this register with the length of the message data (without
10. MDHA does the required algorithm’s auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful
13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from
message digest count from the message digest registers.
step.
previous section.
padding) in bytes.
completion (or failure).
the message digest registers.
Performing a SHA-1 EHMAC
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message
data. This will most likely occur if the MDDSR write is not received
or auto-padding is disabled and a partial message block is provided.
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message
data. This will most likely occur if the MDDSR write is not received
or auto-padding is disabled and a partial message block is provided.
MCF5271 Reference Manual, Rev. 2
NOTE
NOTE
Initialization/Application Information
26-17
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