MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 185
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.4.2
The chip mode is selected during reset and reflected in the MODE field of the reset configuration
register (RCON). See
MCF5271, there is only one valid chip mode setting.
During reset, certain module configurations depend on whether emulation mode is active as
determined by the state of the internal emulation signal.
Freescale Semiconductor
1
2
3
4
5
Modifying the default configurations is possible only if the external RCON pin is asserted.
The D[31:26, 23:22, 18:17, 15:0] pins do not affect reset configuration.
The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It
must stop driving the data bus pins within one CLKOUT cycle after RSTOUT is negated. To prevent contention with
the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become
outputs until at least one CLKOUT cycle after RSTOUT is negated. RCON must also be negated within one cycle
after RSTOUT is negated.
Default configuration
There is no default configuration for clock mode selection. The actual values for the CLKMOD pins must always be
driven during reset. Once out of reset, the CLKMOD pins have no effect on the clock mode selection.
A[23:21]/CS[6:4]
Pin(s) Affected
Chip Mode Selection
Clock mode
Table 9-8. Configuration During Reset
Table 9-9. Chip Configuration Mode Selection
Section 9.3.3.2, “Reset Configuration Register (RCON).”
RCON[9:8] = 00
Configuration
Chip Configuration
No default
Default
MCF5271 Reference Manual, Rev. 2
Master mode
Reserved
Mode
5
CLKMOD1, CLKMOD0
Override Pins
in Reset
D[25:24]
D16 driven high
RCON[MODE]
D16 driven low
00
01
10
11
00
10
01
11
2,3
1
(Continued)
External clock mode (PLL disabled)
Normal PLL mode with external
Chip Select Configuration
Normal PLL mode w/crystal
PADDR[7:5] = A[23:21]
PADDR[6:5] = A[22:21]
PADDR[7:6] = CS[6:5]
PADDR[7:5] = CS[6:4]
PADDR[5] = A[21]
PADDR[7] = CS6
clock reference
1:1 PLL mode
Clock Mode
Function
reference
Functional Description
4
For the
9-9
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