MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 590

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
Breakpoint registers must be carefully configured in a development system if the processor is
executing. The debug module contains no hardware interlocks, so TDR should be disabled while
breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This
prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while
the CPU is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM commands. In
Revision A, if the processor is executing a tight loop that is contained within a single aligned
longword, the processor may never grant the internal bus to the debug module, for example:
label1: nop
or
label2: bra.w label2
The processor grants the internal bus if these loops are forced across two longwords.
30.7
This section specifies the ColdFire processor and debug module’s generation of the processor
status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA
output for an instruction is defined as follows:
where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or both).
A PST value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the
DDATA output {1, 2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions,
CSR[BTB] provides the capability to display the target instruction address on the DDATA output
{2, 3, or 4 bytes} using a PST value of {0x9, 0xA, or 0xB}.
30.7.1 User Instruction Set
Table 30-23
{Dn, An} register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the
destination operand. For a given instruction, the optional operand data is displayed only for those
effective addresses referencing memory. The ‘DD’ nomenclature refers to the DDATA outputs.
30-40
align4
bra.b label1
align4
Processor Status, DDATA Definition
shows the PST/DDATA specification for user-mode instructions. Rn represents any
PST = 0x1, {PST = [0x89B], DDATA= operand}
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor