MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 413

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

22.2.7 DMA Timer Extended Mode Registers (DTXMRn)
DTXMRn, shown in
Freescale Semiconductor
Bits
Bits
2–1
5
4
3
0
7
Figure 22-3. DMA Timer Extended Mode Registers (DTXMRn)
DMAEN
Name
Name
ORRI
Address
FRR
RST
CLK
OM
Reset
Table 22-2. DTMRn Field Descriptions (Continued)
Figure
W
R DMAEN
Output mode.
0 Active-low pulse for one system clock cycle (13-ns resolution at 75 MHz).
1 Toggle output.
Output reference request, interrupt enable. If ORRI is set when DTERn[REF] = 1, a DMA
request or an interrupt occurs, depending on the value of DTXMRn[DMAEN] (DMA request
if =1, interrupt if =0).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request
1 Enable DMA request or interrupt upon reaching the reference value.
Free run/restart
0 Free run. Timer count continues to increment after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
Input clock source for the timer
00 Stop count
01 System clock divided by 1
10 System clock divided by 16. Note that this clock source is not synchronized with the
11 DTINn pin (falling edge)
Reset timer. Performs a software timer reset similar to an external reset, although other
register values can still be written while RST = 0. A transition of RST from 1 to 0 resets
register values. The timer counter is not clocked unless the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
DMA request. Enables DMA request output on counter reference match or capture edge
0 DMA request disabled
1 DMA request enabled
IPSBAR + 0x00_0402 (DTXMR0); IPSBAR + 0x00_0442 (DTXMR1);
IPSBAR + 0x00_0482 (DTXMR2); IPSBAR + 0x00_04C2 (DTXMR3)
or interrupt on capture function).
0
Table 22-3.
event.
7
timer; thus successive time-outs may vary slightly.
22-3, program DMA request and increment modes for the timers.
6
0
0
MCF5271 Reference Manual, Rev. 2
DTXMR
0
0
5
0
0
4
n Field Descriptions
Description
Description
0
0
3
0
0
2
0
0
1
MODE16
Memory Map/Register Definition
0
0
22-5