MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 617

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Ethernet
Freescale Semiconductor
address recognition 19-40
block diagram 19-2
buffer descriptors
collision handling 19-46
errors
frame reception 19-39
frame transmission 19-38
hash table 19-42
initialization 19-35
memory map 19-6
operation
registers
receive (RxBD) 19-31
transmit (TxBD) 19-33
handling 19-47
reception
transmission
10 Mbps 7-Wire 19-5
10 Mbps and 100 Mbps MII 19-37
full duplex 19-4
half duplex 19-4
loopback 19-46
low-power modes 8-9
control (ECR) 19-13
descriptor group upper/lower address
descriptor individual upper/lower
descriptor individual upper/lower address
FIFO receive bound (FRBR) 19-25
FIFO receive start (FRSR) 19-26
FIFO transmit FIFO watermark (TFWR) 19-25
interrupt event (EIR) 19-9
interrupt mask (EIMR) 19-10
MIB control (MIBC) 19-17
MII management frame (MMFR) 19-14
MII speed control (MSCR) 19-16
opcode/pause duration (OPD) 19-21
physical address low (PALRn) 19-20
physical address low/high (PALR, PAUR) 19-20
receive buffer size (EMRBR) 19-28
receive control (RCR) 19-18
receive descriptor active (RDAR) 19-11
CRC 19-48
frame length 19-48
non-octet 19-48
overrun 19-48
truncation 19-49
attempts limit expired 19-47
heartbeat 19-48
late collision 19-47
underrun 19-47
(GAUR/GALR) 19-24
(IAUR/IALR) 19-23
(IAUR/IALR) 19-22
,
19-45
,
19-37
MCF5271 Reference Manual, Rev. 2
Exceptions
External interface module (EIM), see bus
F
Fault-on-fault 3-16
FEC, see Ethernet
G
GPIO
I
I
2
C
access error 3-13
divide-by-zero 3-14
exception stack frame 3-11
format error 3-15
illegal instruction 3-13
overview 3-9
privilege violation 3-14
reset 3-16
trace 3-14
TRAP instruction 3-15
block diagram 12-2
memory map 12-9
operation
registers
arbitration procedure 25-6
clock
handshaking 25-8
memory map 25-8
operation 25-3
programming examples
registers
receive descriptor ring start (ERDSR) 19-27
transmit buffer descriptor ring start (ETSDR) 19-27
transmit control (TCR) 19-19
transmit descriptor active (TDAR) 19-12
low-power modes 8-9
drive strength control (DSCR_x) 12-27
pin assignment (PARx) 12-18
port clear output data (PCLRR_x) 12-16
port data direction (PDDR_x) 12-12
port output data (PODR_x) 12-10
port pin data/set data (PPDSDR_x) 12-14
arbitration 25-6
stretching 25-8
synchronization 25-6
low-power modes 8-7
initialization 25-13
repeated START generation 25-16
START generation 25-14
STOP generation 25-15
Index-3