MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 257

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL)
The INTFRCH and INTFRCL registers are each 32 bits in size and provide a mechanism to allow
software generation of interrupts for each possible source for functional or debug purposes. The
system design may reserve one or more sources to allow software to self-schedule interrupts by
forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRC
register. The assertion of an interrupt request via the INTFRC register is not affected by the
interrupt mask register. The INTFRC register is cleared by reset.
Freescale Semiconductor
Address
Reset
Reset
31–1
Bits
0
W
W
R
R
31
15
1
1
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRL bit
MASKALL Mask all interrupts. Setting this bit will force the other 63 bits of the IMRH and IMRL to ones,
Name
30
14
1
1
Figure 13-4. Interrupt Mask Register Low (IMRL)
29
13
1
1
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRL bit reflects the state of the interrupt signal even if the corresponding IMRL bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
disabling all interrupt sources, and providing a global mask-all capability.
28
12
1
1
Table 13-7. IMRL Field Descriptions
27
11
1
1
MCF5271 Reference Manual, Rev. 2
26
10
1
1
25
IPSBAR + 0x00_0C0C
1
1
9
INT_MASK
INT_MASK
24
1
1
8
23
1
1
7
Description
22
1
1
6
21
1
5
1
20
1
1
4
Memory Map/Register Definition
19
1
1
3
18
1
1
2
17
1
1
1
MASK
ALL
16
1
1
0
13-9