MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 120

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Cache
5.1.3.2
For every memory reference the ColdFire core or the debug module generates, a set of “effective
attributes” is determined based on the address and the access control registers (ACRs). This set of
attributes includes the cacheable/noncacheable definition, the precise/imprecise handling of
operand write, and the write-protect capability.
In particular, each address is compared to the values programmed in the ACRs. If the address
matches one of the ACR values, the access attributes from that ACR are applied to the reference.
If the address does not match either ACR, then the default value defined in the cache control
register (CACR) is used. The specific algorithm is as follows:
if (address == ACR0_address including mask)
5.1.3.3
The cache does not monitor ColdFire core data references for accesses to cached instructions.
Therefore, software must maintain instruction cache coherency by invalidating the appropriate
cache entries after modifying code segments if instructions are cached.
The cache invalidation can be performed in several ways. For the instruction- or data-only
configurations, setting CACR[CINV] forces the entire cache to be marked as invalid. The
invalidation operation requires 512 cycles because the cache sequences through the entire tag
array, clearing a single location each cycle. For the split configuration, CACR[INVI] and
CACR[INVD] can be used in addition to CACR[CINV] to clear the entire cache, only the
instruction half, or only the data half. Any subsequent fetch accesses are postponed until the
invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is
executed, the cache entry defined by bits [12:4] of the source address register is invalidated,
provided CACR[CPDI] is cleared. For the split data/instruction cache configuration, software
directly controls bit 12 which selects whether an instruction cache or data cache line is being
accessed.
These invalidation operations can be initiated from the ColdFire core or the debug module.
5-4
else if (address == ACR1_address including mask)
Effective Attributes = ACR0 attributes
else Effective Attributes = CACR default attributes
Memory Reference Attributes
Cache Coherency and Invalidation
Effective Attributes = ACR1 attributes
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor