MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 101
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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if MACSR[6:5] == -1/* signed fractional mode */
if MACSR[6:5] == 10/* unsigned integer mode */
The four accumulators are represented as an array, ACCn, where n selects the register.
Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC
instructions have an effective issue rate of 1 cycle, regardless of input operand size or type.
All arithmetic operations use register-based input operands, and summed values are stored
internally in an accumulator. Thus, an additional move instruction is needed to store data in a
general-purpose register. One new feature found in EMAC instructions is the ability to choose the
upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if
one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit
multiply accumulates can be performed without fetching additional operands between instructions
by alternating the word choice during the calculations.
The EMAC has four accumulator registers versus the MAC’s single accumulator. The additional
registers improve the performance of some algorithms by minimizing pipeline stalls needed to
store an accumulator value back to general-purpose registers. Many algorithms require multiple
calculations on a given data set. By applying different accumulators to these calculations, it is
often possible to store one accumulator without any stalls while performing operations involving
a different destination accumulator.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in
DSP engines. New and existing ColdFire instructions can accommodate these requirements. A
MOVEM instruction can move large blocks of data efficiently by generating line-sized burst
references. The ability to simultaneously load an operand from memory into a register and execute
a MAC instruction makes some DSP operations such as filtering and convolution more
manageable.
The programming model includes a 16-bit mask register (MASK), which can optionally be used
to generate an operand address during MAC + MOVE instructions. The application of this register
with auto-increment addressing mode supports efficient implementation of circular data queues
for memory operands.
The additional MAC status register (MACSR) contains a 4-bit operational mode field and
condition flags. Operational mode bits control whether operands are signed or unsigned and
whether they are treated as integers or fractions. These bits also control the overflow/saturation
mode and the way in which rounding is performed. Negative, zero, and multiple overflow
condition flags are also provided.
Freescale Semiconductor
Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]}
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
MCF5271 Reference Manual, Rev. 2
General Operation
4-5
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