MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 429

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or
setting QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended
because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and
stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After
QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After
the QSPI stops, QDLYR[SPE] can be cleared.
23.3 Memory Map/Register Definition
Table 23-3
23.3.1 QSPI Mode Register (QMR)
The QMR, shown in
Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer
size are determined by this register. The data output high impedance enable, DOHIE, controls the
operation of QSPI_DOUT between data transfers. When DOHIE is cleared, QSPI_DOUT is
actively driven between transfers. When DOHIE is set, QSPI_DOUT assumes a high impedance
state.
Freescale Semiconductor
is the QSPI register memory map. Reading reserved locations returns zeros.
1
0x00_034C
0x00_0340
0x00_0344
0x00_0348
0x00_0350
0x00_0354
Because the QSPI does not operate in slave mode, the master mode
enable bit, QMR[MSTR], must be set for the QSPI module to operate
correctly.
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Write accesses to these reserved address spaces and reserved register bits have no effect.
IPSBAR
Offset
Figure
QSPI Delay Register (QDLYR)
QSPI Address Register (QAR)
QSPI Interrupt Register (QIR)
QSPI Mode Register (QMR)
QSPI Wrap Register (QWR)
[31:24]
QSPI Data Register (QDR)
23-3, determines the basic operating modes of the QSPI module.
MCF5271 Reference Manual, Rev. 2
Table 23-3. QSPI Registers
[23:16]
NOTE
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
Memory Map/Register Definition
[7:0]
23-9