MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 583

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Command Sequence:
Operand Data:
Result Data:
BDM Accesses of the Stack Pointer Registers (A7: SSP, USP)
The V2 core of the MCF5271supports two unique stack pointer (A7) registers: the supervisor stack
pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
programmable-visible 32-bit registers does not uniquely identify one as the SSP and the other as
the USP. Rather, the hardware uses one 32-bit register as the currently-active A7 and the other
register is named simply the “other_A7”. Thus, the contents of the two hardware registers is a
function of the operating mode of the processor:
if SR[S] = 1
Freescale Semiconductor
then
else
RCREG
???
A7 = Supervisor Stack Pointer
other_A7 = User Stack Pointer
A7 = User Stack Pointer
other_A7 = Supervisor Stack Pointer
’NOT READY’
The only operand is the 32-bit Rc control register select field.
Control register contents are returned as a longword, most-significant word
first. The implemented portion of registers smaller than 32 bits is
guaranteed correct; other bits are undefined.
MS ADDR
0x80A
0x80B
0x80E
0xC04
0x808
0x809
0x80F
Rc
Figure 30-34.
Table 30-20. Control Register Map
MCF5271 Reference Manual, Rev. 2
’NOT READY’
MAC Accumulator 2,3 Extension Bytes (ACCEXT23)
MS ADDR
RCREG
RAM Base Address Register 0 (RAMBAR0)
MAC Accumulator 1 (ACC1)
MAC Accumulator 2 (ACC2)
MAC Accumulator 3 (ACC3)
Command Sequence
Program Register (PC)
Status Register (SR)
Register Definition
REGISTER
CONTROL
READ
’NOT READY’
MS RESULT
NEXT CMD
BERR
XXX
XXX
Background Debug Mode (BDM)
’NOT READY’
LS RESULT
NEXT CMD
NEXT CMD
30-33