MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 45

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1.3.5
1.3.5.1
The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte
instruction cache, an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The
configuration is software-programmable by control bits within the privileged Cache Configuration
Register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory,
organized as 512 lines, each containing 16 bytes of data. The memories consist of a 512-entry tag
array (containing addresses and control bits) and a 8-Kbyte data array, organized as 2048 x 32 bits.
If the desired address is mapped into the cache memory, the output of the data array is driven onto
the ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped
into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch.
The cache module includes a 16-byte line fill buffer used as temporary storage during miss
processing. For all data cache configurations, the memory operates in write-through mode and all
operand writes generate an external bus cycle.
1.3.5.2
The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core
can access in a single cycle. The location of the memory block can be set to any 64-Kbyte
boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module
is physically connected to the processor's high-speed local bus, it can quickly service core-initiated
accesses or memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported
nature of the SRAM makes it ideal for implementing applications with double-buffer schemes,
where the processor and a DMA device operate in alternate regions of the SRAM to maximize
system performance. As an example, system performance can be increased significantly if
Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to
any processing.
1.3.6
The MCF5271’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE
802.3/Ethernet CSMA/CD media access control and channel interface functions. The FEC
supports connection and functionality for the 10/100 Mbps 802.3 media independent interface
(MII). It requires an external transceiver (PHY) to complete the interface to the media.
Freescale Semiconductor
On-chip Memories
Fast Ethernet Controller (FEC)
Cache
SRAM
MCF5271 Reference Manual, Rev. 2
Features
1-9