MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 367

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.2.4.16 Descriptor Group Upper Address Register (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register
must be initialized by the user.
Freescale Semiconductor
Address
Address
Reset
Reset
Reset
Reset
31–0
Bits
W
W
W
W
R
R
R
R
—
—
Figure 19-16. Descriptor Individual Lower Address Register (IALR)
—
—
31
15
31
15
Figure 19-17. Descriptor Group Upper Address Register (GAUR)
IADDR2
Name
—
—
—
—
30
14
30
14
—
—
—
—
29
13
29
13
The lower 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0
of IADDR2 contains hash index bit 0.
—
—
—
—
28
12
28
12
Table 19-19. IALR Field Descriptions
—
—
—
—
27
27
11
11
MCF5271 Reference Manual, Rev. 2
—
—
—
—
26
10
26
10
25
—
—
25
—
—
9
9
IPSBAR + 0x111C
IPSBAR + 0x1120
GADDR1
GADDR1
—
—
—
—
24
24
IADDR2
IADDR2
8
8
23
—
—
23
—
—
Description
7
7
—
—
—
—
22
22
6
6
—
—
—
—
21
21
5
5
—
—
—
—
20
20
4
4
Memory Map/Register Definition
—
—
—
—
19
19
3
3
—
—
—
—
18
18
2
2
—
—
—
—
17
17
1
1
16
—
—
16
—
—
0
0
19-23