MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 432
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Serial Peripheral Interface (QSPI) Module
23.3.3 QSPI Wrap Register (QWR)
23.3.4 QSPI Interrupt Register (QIR)
Figure 23-7
23-12
Address
Reset
11–8
Bits
7–4
3–0
W
15
14
13
12
R HALT WREN WRTO CSIV
15
0
shows the QIR.
NEWQP
ENDQP
CPTQP
WREN
WRTO
Name
HALT
14
CSIV
0
13
0
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once
it has completed execution of the current command.
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current
1 QSPI chip select outputs return to one when not driven from the value in the current
End of queue pointer. Points to the RAM entry that contains the last transfer description in
the queue.
Completed queue entry pointer. Points to the RAM entry that contains the last command
to have been completed. This field is read only.
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on
initiating a transfer.
Figure 23-6. QSPI Wrap Register (QWR)
entry pointed to by QWR[NEWQP] and continue execution.
command RAM entry during a transfer (that is, inactive state is 0, chip selects are active
high).
command RAM entry during a transfer (that is, inactive state is 1, chip selects are active
low).
12
Table 23-6. QWR Field Descriptions
0
MCF5271 Reference Manual, Rev. 2
11
0
10
ENDQP
0
IPSBAR + 0x00_0348
0
9
0
8
Description
0
7
0
6
CPTQP
5
0
0
4
0
3
Freescale Semiconductor
NEWQP
0
2
0
1
0
0
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