MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 558

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
30.4.3 Address Breakpoint Registers (ABLR, ABHR)
The ABLR and ABHR, shown in
that can be used as part of the trigger. These register values are compared with the address for each
30-8
14–13
12–11
10–8
Bits
6–5
4–3
2–0
15
7
Name
TMM
SZM
TTM
RM
TM
SZ
TT
R
Read/write mask. Setting RM masks R in address comparisons.
Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address
comparisons.
Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address
comparisons.
Read/write. R is compared with the R/W signal of the processor’s local bus.
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01
encoding indicates an external or DMA access (for backward compatibility). These bits
affect the TM bits.
Transfer modifier. Compared with the local bus transfer modifier signals, which give
supplemental information for each transfer type. These bits also define the TM encoding
for BDM memory commands (for backward compatibility).
Table 30-6. AATR Field Descriptions
000
001
010
011
100
101
110
TM
111
Figure
MCF5271 Reference Manual, Rev. 2
Explicit cach line push
User code access
User data access
Supervisor code
Supervisor data
30-6, define regions in the processor’s data address space
(normal mode)
Reserved
Reserved
Reserved
access
access
TT=00
Description
(emulator mode)
Emulator mode
Emulator code
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
access
TT=10
(acknowledge/CPU
Interrupt ack level 1
Interrupt ack level 2
Interrupt ack level 3
Interrupt ack level 4
Interrupt ack level 5
Interrupt ack level 6
Interrupt ack level 7
CPU space access
space transfers)
Freescale Semiconductor
TT=11