MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 146
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Clock Module
7-12
Bits
7
6
5
4
3
2
PLLMODE Clock mode. This bit is determined at reset and indicates which clock mode the system is
PLLREF
PLLSEL
LOCKS
Name
LOCK
LOCF
Table 7-6. SYNSR Field Descriptions (Continued)
utilizing (see
to configure the system clock mode during reset.
0 External clock mode
1 PLL clock mode
PLL mode select. This bit is determined at reset and indicates which mode the PLL
operates in. PLLSEL is cleared in 1:1 PLL mode and external clock mode. See
“Reset Controller
reset.
1 Normal PLL mode (see
0 1:1 PLL mode
PLL clock reference source. Configured at reset and reflects the PLL reference source in
normal PLL mode as shown in
1 Crystal clock reference
0 External clock reference
Sticky indication of PLL lock status. The lock detect function sets the LOCKS bit when the
PLL achieves lock after:
When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains
cleared until one of the three listed events occurs.
Furthermore, reading the LOCKS bit at the same time that the PLL loses lock does not
reflect the current loss-of-lock condition.
In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and 1:1
PLL mode, LOCKS is set after reset.
0 PLL loss-of-lock since last system reset or MFD change or currently not locked due to
1 No unintentional PLL loss-of-lock since last system reset or MFD change
PLL lock status bit. Set when the PLL is locked. PLL lock occurs when the synthesized
frequency is within approximately 0.75 percent of the programmed frequency. The PLL
loses lock when a frequency deviation of greater than approximately 1.5 percent occurs.
Reading the LOCK bit at the same time that the PLL loses lock or acquires lock does not
reflect the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a
condition for releasing reset.
If operating in external clock mode, LOCK remains cleared after reset.
0 PLL not locked
1 PLL locked
Loss-of-clock flag. This bit provides the interrupt request flag. Write a 1 to this bit to clear
the flag. Writing 0 has no effect. Asserting reset will clear the flag. This flag is sticky in the
sense that if clocks return to normal after the flag has been set, the bit will remain set until
cleared by either writing 1 or asserting reset.
0 Interrupt service not requested
1 Interrupt service request
• A system reset
• A write to SYNCR that changes the MFD[2:0] bits
• Frequency modulation is enabled
exit from STOP with FWKUP set
MCF5271 Reference Manual, Rev. 2
Table
Module,” for details on how to configure the system clock mode during
7-7). See
Table
Section 7.4.3, “System Clock Generation,”
Table
7-7)
7-7.
Description
Freescale Semiconductor
for details on how
Chapter 10,
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