MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 565

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DRc[4:0]
Freescale Semiconductor
Reset
Reset
W
W
R
R
28–22/
31–30
15–14
29/13
28/12
26/10
27/11
12–6
25/9
24/8
23/7
22/6
21/5
Bits
31
15
0
0
0
TRC
30
14
0
0
0
Name
TRC
EBL
EDx
—
DI
EBL
EBL
29
13
0
0
Figure 30-11. Trigger Definition Register (TDR)
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
Trigger response control. Determines how the processor responds to a completed trigger
condition. The trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Reserved, should be cleared.
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a
breakpoint trigger. Clearing it disables all breakpoints at that level.
Setting an EDx bit enables the corresponding data breakpoint condition based on the size
and placement on the processor’s local data bus. Clearing all EDx bits disables data
breakpoints.
EDLW
EDWL Lower data word.
EDW
U
EDLL
EDLM
EDUM Upper middle data byte. Low-order byte of the high-order word.
EDUU
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than
the DBR contents.
28
12
0
0
Table 30-15. TDR Field Descriptions
Data longword. Entire processor’s local data bus.
Upper data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper upper data byte. High-order byte of the high-order word.
27
11
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
25
0
0
9
24
0x07
0
0
8
Description
23
0
0
7
22
0
0
6
DI
DI
21
0
0
5
EAI
EAI
Memory Map/Register Definition
20
0
4
0
EAR EAL EPC
EAR EAL EPC
19
0
0
3
18
0
0
2
17
0
0
1
30-15
PCI
PCI
16
0
0
0