MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 225

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.3
Table 12-3
Freescale Semiconductor
0x10_0000
0x10_0004
0x10_0008
0x10_0010
0x10_0014
0x10_0018
IPSBAR
0x000C
0x001C
Offset
SDRAMC clock enable (SD_CKE)
UART2 request-to-send (U2RTS)
SDRAM Chip select 0 (SD_CS0)
UART2 transmit data (U2TXD)
UART2 clear-to-send (U2CTS)
DMA acknowledge 2 (DACK2)
DMA acknowledge 1 (DACK1)
DMA acknowledge 0 (DACK0)
UART2 receive data (U2RXD)
Memory Map/Register Definition
summarizes all the registers in the MCF5271 ports address space.
I
I
Timer output 2 (DT2OUT)
Timer output 1 (DT1OUT)
2
DMA request 2 (DREQ2)
DMA request 1 (DREQ1)
DMA request 0 (DREQ0)
2
C serial clock (I2C_SCL)
C serial data (I2C_SDA)
PODR_UARTH
PDDR_UARTH
PODR_ADDR
Table 12-2. MCF5271 Multiple-Pin Functions (Continued)
PDDR_ADDR
Function
PODR_BS
PDDR_BS
[31:24]
Table 12-3. MCF5271 Ports Module Memory Map
MCF5271 Reference Manual, Rev. 2
PODR_DATAH
PODR_UARTL
PDDR_DATAH
PDDR_UARTL
PODR_CS
Port Data Direction Registers
PDDR_CS
Port Output Data Registers
[23:16]
Direction
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
Reserved
Reserved
PODR_SDRAM
PDDR_SDRAM
PODR_DATAL
PDDR_DATAL
3
2
PODR_QSPI
PDDR_QSPI
[15:8]
I2C_SDA, QSPI_DIN, FEC_MDIO
I2C_SCL, QSPI_CLK, FEC_MDC
SD_CKE, QSPI_CS1
U2RXD, FEC_MDIO
U2TXD, FEC_MDC
Associated Pins
DT3OUT, U1RTS
DT2OUT, DT2IN
DT1OUT, DT1IN
TSIZ1, DT1OUT
TSIZ0, DT0OUT
DT3IN, U1CTS
CS2, SD_CS0
IRQ2, DT2IN
TS, DT2OUT
TEA, DT1IN
TIP, DT0IN
PODR_BUSCTL
PDDR_BUSCTL
PODR_FECI2C
PDDR_FECI2C
PODR_TIMER
PDDR_TIMER
Memory Map/Register Definition
[7:0]
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1
12-9