MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 17

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.1.6
19.1.7
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.4.1
19.2.4.2
19.2.4.3
19.2.4.4
19.2.4.5
19.2.4.6
19.2.4.7
19.2.4.8
19.2.4.9
19.2.4.10
19.2.4.11
19.2.4.12
19.2.4.13
19.2.4.14
19.2.4.15
19.2.4.16
19.2.4.17
19.2.4.18
19.2.4.19
19.2.4.20
19.2.4.21
19.2.4.22
19.2.4.23
19.2.5
19.2.5.1
19.2.5.2
19.2.5.3
19.3
19.3.1
19.3.1.1
19.3.2
19.3.3
19.3.4
19.3.5
Freescale Semiconductor
Paragraph
Number
Memory Map/Register Definition ................................................................................ 19-5
Functional Description................................................................................................ 19-35
Address Recognition Options ................................................................................... 19-5
Internal Loopback ..................................................................................................... 19-5
High-Level Module Memory Map ........................................................................... 19-5
Register Memory Map .............................................................................................. 19-6
MIB Block Counters Memory Map.......................................................................... 19-6
Register Description ................................................................................................. 19-8
Buffer Descriptors................................................................................................... 19-29
Initialization Sequence............................................................................................ 19-35
User Initialization (Prior to Setting ECR[ETHER_EN])........................................ 19-35
Microcontroller Initialization.................................................................................. 19-36
User Initialization (After Asserting ECR[ETHER_EN]) ....................................... 19-37
Network Interface Options...................................................................................... 19-37
Ethernet Interrupt Event Register (EIR) ............................................................... 19-9
Interrupt Mask Register (EIMR) ........................................................................ 19-10
Receive Descriptor Active Register (RDAR)..................................................... 19-11
Transmit Descriptor Active Register (TDAR) ................................................... 19-12
Ethernet Control Register (ECR)........................................................................ 19-13
MII Management Frame Register (MMFR) ....................................................... 19-14
MII Speed Control Register (MSCR) ................................................................. 19-16
MIB Control Register (MIBC) ........................................................................... 19-17
Receive Control Register (RCR) ........................................................................ 19-18
Driver/DMA Operation with Buffer Descriptors ............................................... 19-29
Ethernet Receive Buffer Descriptor (RxBD)...................................................... 19-31
Ethernet Transmit Buffer Descriptor (TxBD) .................................................... 19-33
Hardware Controlled Initialization ..................................................................... 19-35
Physical Address Low Register (PALR) ........................................................... 19-20
Physical Address High Register (PAUR) .......................................................... 19-21
Opcode/Pause Duration Register (OPD) ........................................................... 19-21
FIFO Transmit FIFO Watermark Register (TFWR) ......................................... 19-25
FIFO Receive Bound Register (FRBR)............................................................. 19-25
FIFO Receive Start Register (FRSR) ................................................................ 19-26
Transmit Control Register (TCR)...................................................................... 19-19
Descriptor Individual Lower Address Register (IALR) .................................... 19-23
Descriptor Group Upper Address Register (GAUR)......................................... 19-23
Descriptor Group Lower Address Register (GALR)......................................... 19-24
Receive Descriptor Ring Start Register (ERDSR) ............................................ 19-27
Transmit Buffer Descriptor Ring Start Registers (ETSDR) .............................. 19-27
Receive Buffer Size Register (EMRBR) ........................................................... 19-28
Descriptor Individual Upper Address Register (IAUR) ................................... 19-22
MCF5271 Reference Manual, Rev. 2
Contents
Title
Number
Page
xvii