MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 299

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16.4.1.3 Chip Select Control Registers (CSCR0–CSCR7)
Each CSCR, shown in
activation of each chip select. Note that to support the external boot chip select, CS0, the CSCR0
reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before
system initialization.
Freescale Semiconductor
Reset: CSCR0
Reset: Other
Address
31–16
CSCRs
Bits
7–1
8
0
W
R
—
15
0
SRWS
Name
BAM
WP
—
V
—
14
0
Figure 16-6. Chip Select Control Registers (CSCRn)
Figure
—
Base address mask. Defines the chip select block by masking address bits. Setting a BAM
bit causes the corresponding CSAR bit to be ignored in the decode.
0 Corresponding address bit is used in chip select decode.
1 Corresponding address bit is a don’t care in chip select decode.
The block size for CS[7:0] is 2
CSMR[BAM]) + 16. For example, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0001, CS0
addresses a 128-Kbyte (2
access 32 Mbytes (2
access 16 Mbytes (2
CSAR0 = 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and
CSMR1[BAM] = 0x00FF.
Write protect. Controls write accesses to the address range in the corresponding CSAR.
Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the
appropriate chip select not being selected and an access error exception will occur.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed.
Reserved, should be cleared.
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are
valid. Programmed chip selects do not assert until V is set (except for CS0, which acts as
the global chip select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
13
1
Table 16-6. CSMRn Field Descriptions
IPSBAR + 0x00_00A2 (CSCR2); IPSBAR + 0x00_00AE (CSCR3);
IPSBAR + 0x00_00BA (CSCR4); IPSBAR + 0x00_00C6 (CSCR5);
IPSBAR + 0x00_008A (CSCR0); IPSBAR + 0x00_0096 (CSCR1);
IPSBAR + 0x00_00D2 (CSCR6); IPSBAR + 0x00_00DE (CSCR7)
16-6, controls the auto-acknowledge, port size, burst capability, and
—
12
1
IWS
MCF5271 Reference Manual, Rev. 2
—
11
1
—
25
10
24
1
bytes) of address space starting at location 0x0000, and for CS1 to
bytes) of address space starting after the CS0 space, then
17
—
0
0
9
byte) range from 0x0000–0x1_FFFF. Likewise, for CS0 to
n
where n = (number of bits set in respective
AA
—
8
1
Description
—
0
7
PS
—
6
0
BEM BSTR BSTW
—
0
5
—
4
0
Memory Map/Register Definition
—
3
0
—
2
0
SWWS
—
0
1
—
0
0
16-9