MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 311

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The write cycle timing diagram is shown in
Table 17-4
17.5.5 Fast Termination Cycles
Two clock cycle transfers are supported on the MCF5271 bus. In most cases, this is impractical to
use in a system because the termination must take place in the same half-clock during which TS
is asserted. As this is atypical, it is not referred to as the zero-wait-state case but is called the
fast-termination case. Fast termination cycles occur when the external device or memory asserts
TA less than one clock after TS is asserted. This means that the MCF5271 samples TA on the rising
Freescale Semiconductor
A[31:0], TSIZ[1:0]
describes the six states of a basic write cycle.
1.
2.
3.
4.
5.
6.
1.
2.
1.
CSn, BSn
CLKOUT
Set R/W to write
Place address on A[31:0]
Assert TIP and TSIZ[1:0]
Assert TS
Place data on D[31:0]
Negate TS
Sample TA low
Stop driving data from D[31:0]
Start next cycle
D[31:0]
R/W
TIP
TS
TA
MCF5271
Figure 17-8. Basic Write Bus Cycle
Figure 17-7. Write Cycle Flowchart
MCF5271 Reference Manual, Rev. 2
S0
Figure
S1
17-8.
S2
Write
1.
2.
3.
1.
S3
Decode address
Store data on D[31:0]
Assert TA
Negate TA
S4
System
S5
Data Transfer Operation
17-9