MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 505

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

26.2.10 MDHA Message Digest Registers 1 (MDx1)
The MDHA message digest registers 1 consist of five 32-bit digest registers (MDA1, MDB1,
MDC1, MDD1, and MDE1). These registers store the OPAD resulted digest to be used for the
second hash operation in the HMAC or EHMAC mode. This digest is written directly to the
message digest registers 0 after the first hash has been completed. The registers are write only and
any attempts to read from them will always return the value zero.
26.3
The MDHA module consists of three sub-blocks: the FIFO, MDHA Top Control block, and the
MDHA Logic block. A block level diagram of the MDHA module is shown in
Freescale Semiconductor
Address
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Functional Description
31
IPSBAR + 0x19_0078 (MDC1); IPSBAR + 0x19_007C (MDD1); IPSBAR + 0x19_0080 (MDE1)
Figure 26-10. MDHA Message Digest Registers 1 (MDx1)
Internal Bus Clock (f
Address/Data
IPSBAR + 0x19_0070 (MDA1); IPSBAR + 0x19_0074 (MDB1);
Figure 26-11. MDHA Block Diagram
sys/2
MDHA Logic
)
MCF5271 Reference Manual, Rev. 2
Auto-padder
Interface
Control
MDA1, MDB1, MDC1, MDD1, MDE1
MDHA Top Control
FIFO (16x32bit)
Address Decoder
Engine Control
Status Interrupt
Hashing
Hashing
Engine
To Interrupt
Controller
Figure
Functional Description
26-11.
0
26-13