MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 294

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Select Module
Table 16-2
16.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 16.4.1.3 for
more information.
byte strobe control lines (BS[3:0]). Note that all byte lanes are driven, although the state of unused
byte lanes is undefined.
16.3.2 Enhanced Wait State Operation
The chip-select logic has been enhanced to add the notion of secondary wait-state counter values
to be used after the initial wait-state value (where the existing wait state field becomes the initial
access wait state) is applied to the first access. Two fields in the Chip-Select Control Registers
16-4
Number of CSCR Matches
shows the type of access as a function of match in the CSARs and DACRs.
Figure 16-1. Connections for External Memory Port Sizes
Table 16-2. Accesses by Matches in CSARs and DACRs
Multiple
Multiple
Multiple
Figure 16-1
0
1
0
1
0
1
32-bit port
16-bit port
8-bit port
data bus
External
memory
memory
memory
shows the correspondence between the data bus and the external
MCF5271 Reference Manual, Rev. 2
Number of DACR Matches
D[31:24]
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
BS3
Multiple
Multiple
Multiple
0
0
0
1
1
1
D[23:16]
Byte 1
Byte 1
Byte 3
BS2
Driven, undefined
D[15:8]
Byte 2
Driven, undefined
BS1
External, burst-inhibited, 32-bit
Byte 3
D[7:0]
Defined by DACRs
BS0
Defined by CSAR
Type of Access
Undefined
Undefined
Undefined
Undefined
Undefined
External
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