MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 441

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.2
Figure 24-1
An internal interrupt request signal is provided to notify the interrupt controller of an interrupt
condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level and priority
are programmed in the interrupt controller
UART2. See
Note that the UARTs can also be configured to automatically transfer data by using the DMA
rather than interrupting the core. When there is data in the receiver FIFO or when the transmit
holding register is empty, a DMA request can be issued. For more information on generating DMA
requests, refer to
Section 14.3.1, “DMA Request Control
Table 24-1
Figure 24-2
Freescale Semiconductor
• False-start bit detection
• Line-break detection and generation
• Detection of breaks originating in the middle of a character
• Start/end break interrupt/status
Transmitter Serial
Data Output
(UnTXD)
Receiver Serial
Data Input
(UnRXD)
Clear-to- Send
(UnCTS)
Request-to-Send
(UnRTS)
Signal
External Signal Description
briefly describes the UART module signals.
shows both the external and internal signal groups.
shows a signal configuration for a UART/RS-232 interface.
Section 13.2.1.6, “Interrupt Control Register (ICRx, (x = 1, 2,..., 63)).”
The terms ‘assertion’ and ‘negation’ are used to avoid confusion
between active-low and active-high signals. ‘Asserted’ indicates that
a signal is active, independent of the voltage level; ‘negated’ indicates
that a signal is inactive.
Section 24.4.6.1.2, “Setting up the UART to Request DMA
UnTXD is held high (mark condition) when the transmitter is disabled, idle, or operating in the
local loop-back mode. Data is shifted out on UnTXD on the falling edge of the clock source, with
the least significant bit (lsb) sent first.
Data received on UnRXD is sampled on the rising edge of the clock source, with the lsb
received first.
This input can generate an interrupt on a change of state.
This output can be programmed to be negated or asserted automatically by either the receiver
or the transmitter. When connected to a transmitter’s UnCTS, UnRTS can control serial data
flow.
Table 24-1. UART Module Signals
MCF5271 Reference Manual, Rev. 2
(DMAREQC).”
—
ICR13 for UART0, ICR14 for UART1, and ICR15 for
NOTE
Description
External Signal Description
Service,” and
24-3