MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 514
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Random Number Generator (RNG)
27.2.2 RNG Status Register (RNGSR)
The RNGSR, shown in
RNG.
27-2
31–4
Bits
3
2
1
0
Address
Reset
Reset
W
W
R
R
Name
31
15
0
0
0
0
GO
HA
IM
—
CI
30
14
0
0
0
0
Figure
Figure 27-1. RNG Control Register (RNGCR)
Reserved
Clear interrupt. Writing a one to this bit clears the error interrupt and RNGSR[EI].
0 Do not clear error interrupt.
1 Clear error interrupt.
Interrupt mask.
0 Error interrupt is enabled.
1 Error interrupt is masked.
High assurance. Notifies core when FIFO underflow has occurred (FIFO is read while
empty). Enables the Security Violation bit in the RNGSR. Bit is sticky and can only be
cleared by hardware reset.
0 Disable security violation notification.
1 Enable security violation notification.
Go bit. Starts/stops random data from being generated. Bit is sticky and can only be
cleared by hardware reset.
0 FIFO is not loaded with random data.
1 FIFO will be loaded with random data.
29
13
0
0
0
0
Table 27-2. RNGCR Field Descriptions
28
12
27-2, is a read only register which reflects the internal status of the
0
0
0
0
MCF5271 Reference Manual, Rev. 2
27
11
0
0
0
0
26
10
0
0
0
0
IPSBAR + 0x1A_0000
25
0
0
0
0
9
24
0
0
0
0
8
23
0
0
0
0
7
Description
22
0
0
0
0
6
21
0
0
0
0
5
20
0
0
0
0
4
CI
19
0
0
0
3
IM
18
0
0
0
2
Freescale Semiconductor
HA
17
0
0
0
1
GO
16
0
0
0
0
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