MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 287
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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15.4.1 Register Description
The EPORT programming model consists of these registers:
15.4.1.1 EPORT Pin Assignment Register (EPPAR)
Freescale Semiconductor
• The EPORT pin assignment register (EPPAR) controls the function of each pin
• The EPORT data direction register (EPDDR) controls the direction of each one of the pins
• The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin
• The EPORT data register (EPDR) holds the data to be driven to the pins.
• The EPORT pin data register (EPPDR) reflects the current state of the pins.
• The EPORT flag register (EPFR) individually latches EPORT edge events.
1
2
Address
0x13_0000
0x13_0002
0x13_0004
0x13_0006
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
Writing to reserved address locations has no effect, and reading returns 0s.
Reset
IPSBAR
individually.
individually.
individually.
Offset
W
R
15
0
EPPA7
EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER)
14
0
Figure 15-2. EPORT Pin Assignment Register (EPPAR)
EPORT Data Register (EPDR)
EPORT Flag Register (EPFR)
13
0
EPPA6
Table 15-2. Edge Port Module Memory Map
12
0
Bits 15–8
EPORT Pin Assignment Register (EPPAR)
11
0
EPPA5
MCF5271 Reference Manual, Rev. 2
10
0
IPSBAR + 0x13_0000
0
9
EPPA4
0
8
EPORT Pin Data Register (EPPDR)
0
7
EPPA3
6
0
Reserved
Bits 7–0
0
5
EPPA2
2
0
4
Memory Map/Register Definition
0
3
EPPA1
0
2
Access
0
0
1
S/U
S/U
S
S
1
0
0
0
15-3
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