MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 568

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled
on the rising edge of the processor clock as well as the DSI. DSO is delayed from the
DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events
in the debug module’s serial state machine are based on the processor clock rising edge. DSCLK
must also be sampled low (on a positive edge of CLK) between each bit exchange. The msb is
transferred first. Because DSO changes state based on an internally-recognized rising edge of
DSCLK, DSO cannot be used to indicate the start of a serial transfer. The development system
must count clock cycles in a given transfer. C1–C4 are described as follows:
30.5.2.1 Receive Packet Format
The basic receive packet,
30-18
.
• C1—First synchronization cycle for DSI (DSCLK is high).
• C2—Second synchronization cycle for DSI (DSCLK is high).
• C3—BDM state machine changes state depending upon DSI and whether the entire input
• C4—DSO changes to next value.
16
data transfer has been transmitted.
S
BDM State
PSTCLK
Machine
DSCLK
15
DSO
A
memory-referencing cycle. Otherwise, the debug module can accept a
new serial transfer after 32 processor clock periods.
DSI
14
not-ready
13
Figure 30-12. BDM Serial Interface Timing
Figure
12
Current State
Figure 30-13. Receive BDM Packet
response
Past
11
30-13, consists of 16 data bits and 1 status bit
MCF5271 Reference Manual, Rev. 2
Current
10
C1
can
9
C2
Data Field [15:0]
NOTE
be
8
C3
ignored
7
6
C4
except
5
Next State
4
Current
Next
during
3
Freescale Semiconductor
2
a
1
0