MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 156

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Clock Module
7.4.6.1
The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the
reference and feedback clocks. The reference clock comes from either the crystal oscillator or an
external clock source.
The feedback clock comes from one of the following:
When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is
frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference
clock, the PFD pulses the UP signal. If the falling edge of the feedback clock leads the falling edge
of the reference clock, the PFD pulses the DOWN signal. The width of these pulses relative to the
reference clock depends on how much the two clocks lead or lag each other. Once phase lock is
achieved, the PFD continues to pulse the UP and DOWN signals for very short durations during
each reference clock cycle. These short pulses continually update the PLL and prevent the
frequency drift phenomenon known as dead-banding. “Dead-band” is a term used to describe the
minimum amount of phase error between the reference and feedback clocks that a phase detector
cannot correct.
7-22
• CLKOUT in 1:1 PLL mode
• ICO output divided by two if CLKOUT is disabled in 1:1 PLL mode
• ICO output divided by the MFD in normal PLL mode
EXTAL
Phase and Frequency Detector (PFD)
feedback
reference
clock
Figure 7-10. Frequency Modulated PLL Block Diagram
PFD
Clock Detect
MCF5271 Reference Manual, Rev. 2
Loss of
Detect
Lock
down
up
VDDI / VSSI
LOCK
VDDPLL / VSSPLL
LOC
Charge
Charge
Pump
Pump
MFD
Filter
Modulation
Control
ICO
FM
Freescale Semiconductor
ICO clkout