MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 245

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.3.1.7.3 UART/IRQ Drive Strength Control Register (DSCR_UART)
The DSCR_UART register controls the output drive strengths of the following pins: U2RXD,
U2TXD, U1RTS, U1CTS, U1RXD, U1TXD, U0RTS, U0CTS, U0RXD, U0TXD, and IRQ[7:1].
Freescale Semiconductor
Bits
Bits
7–5
3–1
4
0
7
6
5
4
3
2
Figure 12-41. UART/IRQ Drive Strength Control Register (DSCR_UART)
Address
DSCR_FEC EMDC, EMDIO output drive strength. This bit sets the drive strength on the EMDC and
DSCR_IRQ IRQ drive strength. This bit sets the drive strength on the IRQ[7:1] pins.
DSCR_I2C I2C_SDA, I2C_SCL output drive strength. This bit sets the drive strength on the I2C_SDA
Reset
DSCR_
DSCR_
UART2
UART1
Name
Name
W
—
—
—
—
—
R
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when RCON = 0
Table 12-19. DSCR_FECI2C Field Descriptions
0
0
7
Table 12-20. DSCR_UART Field Descriptions
Reserved, should be cleared.
0 IRQ[7:1] pins set at low drive
1 IRQ[7:1] pins set at high drive
Reserved, should be cleared.
UART2 drive strength. This bit sets the drive strength on the U2RXD and U2TXD pins.
0 U2RXD, U2TXD pins set at low drive
1 U2RXD, U2TXD pins set at high drive
Reserved, should be cleared.
UART1 drive strength. This bit sets the drive strength on the U1RXD, U1TXD, U1CTS, and
U1RTS pins.
0 U1RXD, U1TXD, U1CTS, and U1RTS pins set at low drive
1 U1RXD, U1TXD, U1CTS, and U1RTS pins set at high drive
Reserved, should be cleared.
EMDIO pins.
0 EMDC and EMDIO set at low drive
1 EMDC and EMDIO set at high drive
Reserved, should be cleared.
and I2C_SCL pins.
0 I2C_SDA and I2C_SCL set at low drive
1 I2C_SDA and I2C_SCL set at high drive
See Note
DSCR_
IRQ
6
MCF5271 Reference Manual, Rev. 2
0
0
5
IPSBAR + 0x10_0053
See Note
DSCR_
UART2
4
Description
Description
0
0
3
See Note
DSCR_
UART1
2
1
0
0
Memory Map/Register Definition
See Note
DSCR_
UART0
0
12-29