MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 237

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.3.1.5.3 Byte Strobe Pin Assignment Register (PAR_BS)
The PAR_BS register controls the functions of the byte strobe pins.
12.3.1.5.4 Chip Select Pin Assignment Register (PAR_CS)
The PAR_CS register controls the functions of the EIM chip select pins.
Freescale Semiconductor
Bits
Bits
3–2
1–0
7–4
3–0
Figure 12-32. Byte Strobe Pin Assignment Register (PAR_BS)
PAR_TIP
PAR_BS
PAR_TS
Name
Name
Table 12-10. PAR_BUSCTL Field Descriptions (Continued)
Address
—
Reset
W
R
TS Pin Assignment Field.
The PAR_TS field configures the TS pin for one of its primary functions or GPIO.
0x TS pin configured for GPIO
10 TS pin configured for DMA acknowledge 2 function
11 TS pin configured for external bus TS function
TIP Pin Assignment Field .
The PAR_TIP field configures the TIP pin for one of its primary functions or GPIO.
0x TIP pin configured for GPIO
10 TIP pin configured for DMA request 0 function
11 TIP pin configured for external bus TIP function
Reserved, should be cleared.
BS[3:0] pin assignment. The PAR_BS[3:0] bits configure the BS[3:0] pins for their primary
function or GPIO.
0 BS[3:0] pin configured for GPIO
1 BS[3:0] pin configured for BS[3:0] function
Refer to
configuration.
Table 12-11. PAR_BS Field Descriptions
0
0
7
Chapter 9, “Chip Configuration Module
MCF5271 Reference Manual, Rev. 2
0
0
6
0
0
5
IPSBAR + 0x10_0044
0
0
4
Description
Description
1
3
(CCM)” for more information on reset
2
1
PAR_BS
1
1
Memory Map/Register Definition
1
0
12-21