MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 358
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Fast Ethernet Controller (FEC)
19.2.4.6 MII Management Frame Register (MMFR)
The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is
used to communicate with the attached MII compatible PHY device(s), providing read/write
access to their MII registers. Performing a write to the MMFR will cause a management frame to
be sourced unless the MSCR has been programmed to 0. In the case of writing to MMFR when
MSCR = 0, if the MSCR register is then written to a non-zero value, an MII frame will be
generated with the data previously written to the MMFR. This allows MMFR and MSCR to be
programmed in either order if MSCR is currently zero.
19-14
Address
Reset
Reset
Bits
1
0
W
W
R
R
—
—
31
15
ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible.
ST
RESET
Name
—
—
30
14
Figure 19-7. MII Management Frame Register (MMFR)
—
—
Table 19-8. ECR Field Descriptions (Continued)
29
13
When this bit is cleared, reception is immediately stopped and transmission is stopped
after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s)
for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is
deasserted, the DMA, buffer descriptor, and FIFO control logic are reset, including the
buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by hardware under the
following conditions:
When this bit is set, the equivalent of a hardware reset is performed but it is local to the
FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also, any
transmission/reception currently in progress is abruptly aborted. This bit is automatically
cleared by hardware during the reset sequence. The reset sequence takes approximately
8 system clock cycles after RESET is written with a 1.
OP
• ECR[RESET] is set by software, in which case ETHER_EN will be cleared
• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN will be
cleared
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12
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11
MCF5271 Reference Manual, Rev. 2
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10
PA
25
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9
IPSBAR + 0x1040
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8
DATA
23
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Description
7
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6
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5
RA
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4
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19
3
Freescale Semiconductor
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2
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1
TA
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0
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