MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 323

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.3
The DRAM controller registers memory map is shown in
18.3.1 DRAM Control Register (DCR)
The DCR, shown in
Freescale Semiconductor
Address
Reset
15–14
Bits
13
W
R
Memory Map/Register Definition
0x00_004C
0x00_0040
0x00_0044
0x00_0048
0x00_0050
0x00_0054
15
IPSBAR
0
0
Offset
Name
NAM
14
0
0
—
Figure
NAM COC
—
13
Reserved, should be cleared.
No address multiplexing. Some implementations require external multiplexing. For
example, when linear addressing is required, the SDRAM should not multiplex addresses
on SDRAM accesses.
0 The SDRAM controller multiplexes the external address bus to provide column
1 The SDRAM controller does not multiplex the external address bus to provide column
Figure 18-2. DRAM Control Register (DCR)
DRAM control register (DCR)
addresses.
addresses.
[31:24]
Table 18-3. DRAM Controller Registers
18-2, controls refresh logic.
—
12
Table 18-4. DCR Field Descriptions
—
IS
11
MCF5271 Reference Manual, Rev. 2
DRAM address and control register 0 (DACR0)
DRAM address and control register 1 (DACR1)
—
10
RTIM
DRAM mask register block 0 (DMR0)
DRAM mask register block 1 (DMR1)
[23:16]
—
IPSBAR + 0x00_0040
9
—
8
—
—
Description
7
Table
—
6
[15:8]
18-3.
—
5
RC
—
—
4
Memory Map/Register Definition
—
3
[7:0]
—
2
—
1
—
0
18-5