MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1031

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

in the last data phase. After the final data phase, both PCI_FRAME and PCI_IRDY are negated (the bus
becomes idle).
There are three types of master-initiated termination:
As an initiator, if the PCI controller does not detect the assertion of PCI_DEVSEL within four clock cycles
following the address phase (five clock cycles after asserting PCI_FRAME), it terminates the transaction
with a master-abort.
17.4.2.8.2
By asserting the PCI_STOP signal, a target may request that the initiator terminate the current transaction.
Once asserted, the target holds PCI_STOP asserted until the initiator negates PCI_FRAME. Data may or
may not be transferred during the request for termination. If PCI_TRDY and PCI_IRDY are asserted
during the assertion of PCI_STOP, data is transferred. However, if PCI_TRDY is negated when
PCI_STOP is asserted, it indicates that the target will not transfer any more data; therefore, the initiator
does not wait for a final data transfer as it would in a completion termination.
When a transaction is terminated by PCI_STOP, the initiator must negate its REQn signal for a minimum
of two PCI clock cycles, (one corresponding to when the bus goes to the idle state (PCI_FRAME and
PCI_IRDY negated)). If the initiator intends to complete the transaction, it can reassert its REQn
immediately following the two clock cycles. If the initiator does not intend to complete the transaction, it
can assert REQn whenever it needs to use the PCI bus again.
There are three types of target-initiated termination:
Freescale Semiconductor
•
•
•
•
•
•
Completion—Refers to termination when the initiator has concluded its intended transaction. This
is the most common reason for termination.
Timeout—Refers to termination when the initiator loses its bus grant (GNTn is negated), and its
internal latency timer has expired. The intended transaction is not necessarily concluded.
Master-abort—An abnormal case of master-initiated termination. If no device (including the
subtractive decoding agent) asserts PCI_DEVSEL to claim a transaction, the initiator terminates
the transaction with a master-abort. For a master-abort termination, the initiator negates
PCI_FRAME and then negates PCI_IRDY on the next clock. If a transaction is terminated by
master-abort (except for a special-cycle command), the received master-abort bit (bit 13) of the PCI
bus status register is set.
Disconnect—Disconnect refers to termination requested because the target is temporarily unable
to continue bursting. Disconnect implies that some data has been transferred. The initiator may
restart the transaction at a later time starting with the address of the next untransferred data. (That
is, data transfer may resume where it left off.)
Retry—Retry refers to termination requested because the target is currently in a state where it is
unable to process the transaction. Retry implies that no data was transferred. The initiator may start
the entire transaction over again at a later time. Note that the PCI Local Bus Specification, Rev. 2.2
requires that all retried transactions must be completed.
Target-Abort—Target-abort is an abnormal case of target-initiated termination. Target-abort is
used when a fatal error has occurred or when a target can never respond.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Target-Initiated Termination
PCI Bus Interface
17-53