MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 681

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.4.4.2.1
The following example further illustrates the steps required to perform two writes to the RAM array at
non-sequential addresses assuming that the relevant BRn and ORn registers have been previously setup.
Note that if step 1 (or 6) and 2 (or 7) are reversed, then step 3 (or 8) is replaced by the following:
14.4.4.2.2
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (when MxMR[OP] = 0b10). The following example
further illustrates the steps required to perform two reads from the RAM array at non-sequential addresses
assuming that the relevant BRn and ORn registers have been previously setup.
Freescale Semiconductor
1. Program MxMR for the first write (with desired RAM array address).
2. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
3. Read MDR to ensure that the MDR has already been updated with the desired pattern. (Or, read
4. Preform a dummy write transaction. (Write transaction can now be performed.)
5. Read/check MxMR[MAD]. If incremented, then the previous dummy write transaction is
6. Program MxMR for the second write with the desired RAM array address.
7. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
8. Read MDR to ensure that the MDR has already been updated with the desired pattern.
9. Perform a dummy write transaction.(Write transaction can now be performed.)
10. Read/check MxMR[MAD]. If incremented, then the previous dummy write transaction is
•
1. Program MxMR for the first read with the desired RAM array address.
2. Read MxMR to ensure that the MxMR has already been updated with the desired configuration,
3. Perform a dummy read transaction.(Read transaction can now be performed.)
4. Read/check MxMR[MAD]. If incremented, then the previous dummy read transaction is
5. Read MDR.
6. Program MxMR for the second read with the desired RAM array address.
7. Read MxMR to ensure that the MxMR has already been updated with the desired configuration,
8. Perform a dummy read transaction.(Read transaction can now be performed.)
configuration.
MxMR if step 2 is not performed.)
completed; proceed to step 6. Repeat step 5 until incremented.
configuration.
completed.
Read MxMR to ensure that the MxMR has already been updated with the desired configuration.
such as RAM array address.
completed; proceed to step 5. Repeat step 4 until incremented.
such as RAM array address.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
UPM Programming Example (Two Sequential Writes to the
RAM Array)
RAM Array)
UPM Programming Example (Two Sequential Reads from the
Local Bus Controller
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