MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 963

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA controller to begin the DMA transfer either when SARn is written or when DARn is written,
determined by the state of MRn[CDSM/SWSM]. Writing to SARn initiates the DMA transfer if
MRn[CDSM/SWSM] is set. Writing to DARn initiates the DMA transfer if MRn[CDSM/SWSM] is
cleared. The DMA controller automatically sets the channel start bit, MRn[CS]. Software is expected to
program all the appropriate registers before writing the source or destination address registers. The transfer
is finished after all the bytes specified in the byte count register have been transferred or if an error
condition occurs. The sequence of events to start and complete a transfer in single-write start basic direct
mode is as follows:
16.4.1.1.3
In basic chaining mode, software must first build link descriptor segments in memory. Then the current
link descriptor address register must be initialized to point to the first descriptor in memory. The DMA
controller loads descriptors from memory prior to a DMA transfer. The DMA controller begins the transfer
according to the link descriptor information loaded for the segment. After the current segment is finished,
the DMA controller reads the next link descriptor from memory and begins another DMA transfer. The
transfer is finished if the current link descriptor is the last one in memory or if an error condition occurs.
The sequence of events to start and complete a transfer in chaining mode is as follows:
Freescale Semiconductor
1. Poll the channel state (see
2. Initialize the source attributes (SATRn), DATRn, and BCRn registers.
3. Set the mode register channel transfer mode bit, MRn[CTM], and the single-write start direct mode
4. A write to the source or destination address register starts the DMA transfer and automatically sets
5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
6. SRn[CB] is automatically cleared by the DMA controller after the transfer is finished, or if the
7. End of segment interrupt is generated if MRn[EOSIE] is set.
1. Build link descriptor segments in memory.
2. Poll the channel state (see
3. Initialize CLNDARn and ECLNDARn to point to the first link descriptor in memory.
4. Clear the mode register channel transfer mode bit, MRn[CTM], as well as MRn[XFE], to indicate
5. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.
6. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
7. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
bit, MRn[SRW]. Other control parameters may also be initialized in the mode register. Set
MRn[CDSM/SWSM] for transfers started using SARn. Clear MRn[CDSM/SWSM] for transfers
started using the DARn.
MRn[CS].
transfer is aborted (MRn[CA] transitions from a 0 to 1), or if a transfer error occurs.
basic chaining mode. Other control parameters may also be initialized in the mode register.
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
Basic Chaining Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table
Table
16-21), to confirm that the specific DMA channel is idle.
16-21), to confirm that the specific DMA channel is idle.
DMA Controller
16-27