MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 994

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Bus Interface
17.3.1.2
The outbound address translation and mapping unit controls the mapping of transactions from the internal
platform address space to the external PCI address space. The outbound ATMU consists of four translation
windows plus a default translation for transactions that do not hit in one of the four windows.
Each window contains a base address that points to the beginning of the window in the local address map,
a translation address that specifies the high-order bits of the transaction in the external PCI address space,
and a set of attributes including window size and external transaction type.
Each window must be aligned based on the granularity specified by the window size. If two outbound
ATMU windows overlap in the local address space, the mapping of the lower numbered window has
precedence over the higher numbered window.
Window 0 is the default window and is the only window enabled upon reset. The default outbound register
set is used when a transaction misses in all of the other outbound windows.
17.3.1.2.1
The PCI outbound translation address registers (POTARn) select the starting addresses in the PCI address
space for hits in the PCI outbound windows. The translated address is created by concatenating the
transaction offset to this translation address. The format of the POTARn is shown in
Table 17-7
17.3.1.2.2
The PCI outbound translation extended address registers (POTEARn) contain the most significant bits of
a 64-bit translation address. The format of POTEARn is shown in
17-16
Offset 0xC00, 0xC20, 0xC40, 0xC60, 0xC80
Reset
12–31
0–11
W
Bits Name
R
0
TEA Translation extended address. Represents bits [43:32] of a 64-bit PCI address (bit 0 is lsb).
describes the fields of the POTARn registers.
TA
PCI ATMU Outbound Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Outbound Translation Address Registers (POTAR n )
PCI Outbound Translation Extended Address Registers (POTEAR n )
Translation address. Represents bits [31:12] of the PCI address. Based on the size of the window
specified in POWAR n [OWS], the low-order bits of this field may be ignored.
Figure 17-6. PCI Outbound Translation Address Registers (POTAR n )
TEA
Table 17-7. POTAR n Field Descriptions
11 12
All zeros
Description
Figure
TA
17-7.
Freescale Semiconductor
Figure
Access: Read/Write
17-6.
31