MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 632

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14-14
24–27
Bits
23
28
29
30
31
Name
XACS Extra address to chip-select setup. Setting this bit increases the delay of the LCS n assertion relative to the
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
TRLX Timing relaxed. Modifies the settings of timing parameters for slow memories or peripherals.
SETA External address termination
SCY
EAD
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
address change when the external memory access is handled by the GPCM. After a system reset,
OR0[XACS] = 1.
0 Address to chip-select setup is determined by ORx[ACS].
1 Address to chip-select setup is extended (see
Cycle length in bus clocks. Determines the number of wait states inserted in the bus cycle, when the GPCM
handles the external memory access. Thus it is the main parameter for determining cycle length. The total
cycle length depends on other timing attribute settings. After a system reset, OR0[SCY] = 1111.
0000 No wait states
0001 1 bus clock cycle wait state
...
1111 15 bus clock cycle wait states
0 Access is terminated internally by the memory controller unless the external device asserts LGTA earlier
1 Access is terminated externally by asserting the LGTA external signal. (Only LGTA can terminate the
0 Normal timing is generated by the GPCM.
1 Relaxed timing on the following parameters:
access from the current bank and the next access.
External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
• Adds an additional cycle between the address and control signals (only if ACS ≠ 00)
• Doubles the number of wait states specified by SCY, providing up to 30 wait states
• Works in conjunction with EHTR to extend hold time on read accesses
• LCS n (only if ACS ≠ 00) and LWE signals are negated one cycle earlier during writes.
to terminate the access.
access).
LCRR[EADC]).
TRLX
Table 14-6. OR n
0
0
1
1
EHTR
0
1
0
1
—
GPCM Field Descriptions (continued)
The memory controller generates normal timing. No additional cycles
are inserted.
1 idle clock cycle is inserted.
4 idle clock cycles are inserted.
8 idle clock cycles are inserted.
Description
Table 14-23
and
Meaning
Table
14-24).
Freescale Semiconductor