MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 895

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.6.5.1.3
It is frequently useful to create rules that are guaranteed to succeed or fail, specifically to enforce a default
filing decision or act as null entries. Suggested constructions for such rules are shown in
15.6.5.1.4
The filer can produce two interrupt events in IEVENT. Event FIR indicates an error condition where the
filer was unable to provide a definite result, either because no rule in the table succeeded, or because
frames arrived too rapidly to complete searching of the table. Event FIQ indicates that the filer accepted a
frame to a RxBD ring that was not enabled in RQCTRL (this can also occur if the filer is disabled, but
RxBD ring 0—default queue or FSQEN mode queue—is not enabled). FIQ is also asserted in the case
where no rule in the entire table succeeded. The various combinations of these interrupt events and their
interpretation appear in
15.6.5.1.5
The eTSEC frame parser always provides values for all properties, even where the relevant headers are not
available. In the latter case, the filer is given default properties that can be used to avoid conflict with
normal, defined property values. Accordingly, the rules in the filer table can be partitioned into rule sets
such that if all rules in a given set fail (due to headers being unavailable), lower priority rule sets can be
subsequently searched until either a rule set provides a match or a single default—catch-all—rule specifies
a definite receive queue. For example, an 802.1p priority rule set may be followed by an IP TOS rule set,
Freescale Semiconductor
IEVENT[FIR]
1
2
3
Default file—Always file frame to ring Q
Default reject—Always discard frame
Empty rule in AND—Always matches
Empty rule in rule set—Always fails
Hexadecimal digits qq denotes field Q shifted left 2 bits.
Set CLE = 1 if the empty rule guards a cluster.
Set CLE = 1 if the empty rule occurs at the end of a cluster.
0
0
1
1
Rule Description
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IEVENT[FIQ]
Special-Case Rules
Filer Interrupt Events
Setting Up the Receive Queue Filer Table
0
1
0
1
Table
No error. The filer successfully rejected or filed a frame.
Illegal queue error. The filer accepted a frame to a RxBD ring that is disabled (including ring 0
if filing is disabled).
Partial search error. The filer did not have sufficient time to complete its search of the filer table.
No matching rule error. The filer searched all 256 entries of the filer table without finding a rule
that succeeds.
Table 15-142. Receive Queue Filer Interrupt Events
15-142.
Table 15-141. Special Filer Rules
CLE REJ AND
0/1
0/1
0
0
2
3
0
1
0
0
0
0
1
0
RQCTRL Fields
000_000
000_000
000_000
Q
Q
Description
CMP
01
01
01
11
Enhanced Three-Speed Ethernet Controllers
0000
0000
0000
0000
PID
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0x0000_0000
RQPROP
Word
Table
0x0000_00A0
0x0000_ qq 20
0x0000_0120
0x0000_0060
RQCTRL
Word
15-141.
1
15-165