MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 862

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.6.1.6
This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs and the
eTSEC to implement a reduced-pin count version of a SerDes interface for optical-fiber devices in
1000BASE-SX/LX applications.
signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC
immediately begins auto-negotiation with the SerDes.
A RTBI interface has 15 signals (GE_GTX_CLK125 included), as defined by the RGMII specification
Version 1.2a 9/22/00, and is intended to be an alternative to the IEEE 802.3u MII, the IEEE 802.3z GMII
and the TBI standard for connecting to an Ethernet PHY.
15-132
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
Reduced Ten-Bit Interface (RTBI)
eTSEC
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Data (TSEC n _RXD[4:0]/TSEC n _RXD[9:5])
Transmit Data (TSEC n _TXD[4:0]/TSEC n _TXD[9:5])
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
Figure 15-122. eTSEC-RTBI Connection
Figure 15-122
Receive Clock (TSEC n _RX_CLK)
Management Data Clock1 (MDC)
Management Data I/O1 (MDIO)
depicts the basic components of the RTBI including the
Ethernet
Gigabit
PHY
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