MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 28

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
15.5.3.4.2
15.5.3.4.3
15.5.3.4.4
15.5.3.4.5
15.5.3.5
15.5.3.5.1
15.5.3.5.2
15.5.3.5.3
15.5.3.5.4
15.5.3.5.5
15.5.3.5.6
15.5.3.5.7
15.5.3.5.8
15.5.3.5.9
15.5.3.5.10
15.5.3.5.11
15.5.3.5.12
15.5.3.5.13
15.5.3.5.14
15.5.3.5.15
15.5.3.5.16
15.5.3.6
15.5.3.6.1
15.5.3.6.2
15.5.3.6.3
15.5.3.6.4
15.5.3.6.5
15.5.3.6.6
15.5.3.6.7
15.5.3.6.8
15.5.3.6.9
15.5.3.6.10
15.5.3.6.11
15.5.3.6.12
15.5.3.6.13
15.5.3.6.14
15.5.3.6.15
15.5.3.6.16
xxviii
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MAC Registers .................................................................................................... 15-66
MIB Registers...................................................................................................... 15-79
Controlling CSMA/CD.................................................................................... 15-64
Handling Packet Collisions ............................................................................ 15-64
Controlling Packet Flow.................................................................................. 15-65
Controlling PHY Links.................................................................................... 15-66
MAC Configuration 1 Register (MACCFG1)................................................. 15-66
MAC Configuration 2 Register (MACCFG2)................................................. 15-68
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 15-70
Half-Duplex Register (HAFDUP) ................................................................... 15-71
Maximum Frame Length Register (MAXFRM) ............................................. 15-72
MII Management Configuration Register (MIIMCFG) .................................. 15-72
MII Management Command Register (MIIMCOM)....................................... 15-73
MII Management Address Register (MIIMADD)........................................... 15-74
MII Management Control Register (MIIMCON)............................................ 15-74
MII Management Status Register (MIIMSTAT) ............................................. 15-75
MII Management Indicator Register (MIIMIND)........................................... 15-75
Interface Status Register (IFSTAT).................................................................. 15-76
MAC Station Address Part 1 Register (MACSTNADDR1) ........................... 15-76
MAC Station Address Part 2 Register (MACSTNADDR2) ........................... 15-77
MAC Exact Match Address 1–15 Part 1 Registers
MAC Exact Match Address 1–15 Part 2 Registers
Transmit and Receive 64-Byte Frame Counter (TR64) .................................. 15-79
Transmit and Receive 65- to 127-Byte Frame Counter (TR127) .................... 15-80
Transmit and Receive 128- to 255-Byte Frame Counter (TR255) .................. 15-80
Transmit and Receive 256- to 511-Byte Frame Counter (TR511) .................. 15-81
Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) ................. 15-81
Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)........... 15-82
Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter
Receive Byte Counter (RBYT)........................................................................ 15-83
Receive Packet Counter (RPKT) ..................................................................... 15-83
Receive FCS Error Counter (RFCS) ............................................................... 15-84
Receive Multicast Packet Counter (RMCA) ................................................... 15-84
Receive Broadcast Packet Counter (RBCA) ................................................... 15-85
Receive Control Frame Packet Counter (RXCF) ............................................ 15-85
Receive Pause Frame Packet Counter (RXPF)................................................ 15-86
Receive Unknown Opcode Packet Counter (RXUO)...................................... 15-86
Receive Alignment Error Counter (RALN) .................................................... 15-87
(MAC01ADDR1–MAC15ADDR1)............................................................ 15-78
(MAC01ADDR2–MAC15ADDR2)............................................................ 15-78
(TRMGV) .................................................................................................... 15-82
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