MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 628

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
1
14.3.1
This section provides a detailed description of the LBC configuration, status, and control registers with
detailed bit and field descriptions.
Address offsets in the LBC address range that are not defined in
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has
no effect.
14.3.1.1
The base registers (BRn), shown in
memory bank. The memory controller uses this information to compare the address bus value with the
current address accessed. Each register (bank) includes a memory attribute and selects the machine for
memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR7[V] are cleared, and
the value of BR0[PS] reflects the initial port size configured by the boot ROM location signals.
14-10
Reset BR1–BR7
Port size for BR0 is configured from external signals during reset, hence ‘ nn ’ is either 0x08, 0x10, or 0x18. See
“Boot ROM
0x0BC
Offset
0x0C0
0x0D0
0x0D4
0x0B8
Reset BR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Offset 0x000 (BR0)
LTEIR—Transfer error interrupt register
LTEATR—Transfer error attributes register
LTEAR—Transfer error address register
LBCR—Configuration register
LCRR—Clock ratio register
Location,” for more information.
Register Descriptions
W
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
R
Base Registers (BR0–BR7)
0x008 (BR1)
0x010 (BR2)
0x018 (BR3)
1 BR0 has its valid bit set during reset. Thus bank 0 is valid with the port size (PS) configured from external
0
boot ROM configuration signals during reset. (See
information.) All other base registers have all bits cleared to zero during reset.
Table 14-3. Local Bus Controller Memory Map (continued)
Use
Figure 14-2. Base Registers (BR n )
Figure
BA
0x020 (BR4)
0x028 (BR5)
0x030 (BR6)
0x038 (BR7)
14-2, contain the base address and address types for each
All zeros
16 17 18 19 20 21 22
Section 4.4.3.4, “Boot ROM
XBA
0
Access
Table 14-3
R/W
R/W
R/W
R/W
R/W
n n 0
PS DECC WP MSEL — ATOM — V
0
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x8000_0008
should not be accessed for
Reset
23 24
0
0 0 0 0 0
Freescale Semiconductor
Location,” for more
Access: Read/Write
26 27 28 29 30 31
14.3.1.12/14-26
14.3.1.13/14-27
14.3.1.14/14-29
14.3.1.15/14-29
14.3.1.16/14-30
Section/Page
Section 4.4.3.4,
0 0 1
1