MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 902

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
result in the hardware failing to maintain back pressure on the far end. Upon software incrementing
RFBPTRn a subsequent time, the wrap condition will be successfully detected and hardware will
recognize a nearly full ring (rather than a nearly empty one). Since software can increment RFBPTRn by
any amount, it is not possible for hardware to determine in this case whether the user has cleared the entire
ring or just one BD. Users can eliminate the possibility of this condition occurring by ensuring that
RFBPTRn is incremented by at least two BDs each time (i.e. clear at least two buffers whenever the RxBD
unload routine is called).
Once the eTSEC determines that this threshold has been reached, back pressure will be applied
accordingly. The type of back pressure that is applied will vary according to the physical interface that is
used.
15.6.6.2
15.6.6.2.1
Software configures RBASEn and RQPRMn[LEN] according to the parameters for that ring. Then the
number of free BDs that are required to prevent the eTSEC from automatically asserting flow control are
programmed in RQPRM[FBTHR]. The receiver is then enabled.
Note: the act of programming RBASEn will initialize RFBPTRn to the start of the of the ring. When the
ring is in this initial empty state, there is no concept of a last freed BD. In this case, the calculated number
of free BDs is the size of the ring. Since the BD that the hardware is currently pointing to is to be
considered in-use, the free BD count is actually one higher than the total available. As soon as the hardware
consumes a BD (by writing it back to memory), RBPTRn will advance and the free BD count will
15.6.6.2.2
As software frees BDs from the ring, it writes the physical address of the BD just freed to RFBPTRn. The
eTSEC will assert flow control if the distance (using modulo arithmetic) between RBPTRn and RFBPTRn
is < RQPRMn[FBTHR]. In multi-ring operation, if the free BD count of any active ring drops below the
threshold for that ring, flow control will be asserted. Once enough BDs are freed for all active rings to meet
their respective free BD thresholds, application of back pressure will cease.
15-172
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Half duplex Ethernet: No support in this mode.
Full duplex Ethernet: An IEEE 802.3 PAUSE frame (see sect. 15.6.3.9/15-151) will be issued as
if the TCTRL[TFC_PAUSE] bit was set. An internal counter will track the time the far end
controller is expected to remain in pause (based on the setting of PTV[PT]). When that counter
reaches half the value of PTV[PT], the eTSEC will reissue a pause frame if the free BD calculation
for any ring is below the threshold for that ring. For example, if PTV[PT] is set to 10 quanta, a pause
frame will be re-issued when five quanta have elapsed if the free BD threshold is still not met. A
practical minimum for PTV[PT] of 4 quanta is recommended.
FIFO packet interface: Link layer flow control will be asserted via use of the RFC signal (CRS
pin). Flow control will be asserted for the entire time that free BD threshold is not met. The same
mechanism is used for both GMII-style and encoded packet modes.
Software Use of Hardware-Initiated Back Pressure
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Initialization
Operation
Freescale Semiconductor