MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 571

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 12-50
Freescale Semiconductor
32–54
0–29
Bits
30
31
55
56
57
58
59
60
CDWE Channel done writeback enable.
AWSE Always writeback status enable.
Name
IWSE ICV writeback status enable.
CON
EAE
BS
—
—
—
R
describes the CCCRs.
Table 12-50. Crypto-Channel Configuration Register (CCCR) Field Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved. Set to zero.
Continue.
0 No special action.
1 Causes the same channel reset actions as bit R, except that the fetch FIFO and the lower half of the CCR
Reset channel.
0 No special action.
1 Causes a software reset of the channel, clearing all its internal state. The details of the software reset
actions depend upon what the channel is doing when the bit is set:
If the R bit is set while the channel is requesting an EU assignment from the controller, the channel cancels its
request by asserting the release output signals. The channel then resets all its registers, clears the R bit, and
returns the channel state machine to the idle state.
If the R bit is set after the channel has been assigned an EU, the channel requests a write from the controller
to set the software reset bit of the EU. If a secondary EU has been reserved, the channel requests a write to
reset that EU as well. The channel next asserts the appropriate release signal to notify the controller that the
channel has finished with the reserved EU(s). The channel then resets all the registers, clears the RESET bit
and returns the channel state machine to the idle state.
Reserved. Set to zero.
Burst size. The SEC accesses long text-data parcels in main memory through bursts of programmable size:
0 Burst size is 64 bytes
1 Burst size is 128 bytes
0 No special action.
1 If the descriptor calls for ICV comparison, then at the completion of descriptor processing, write back the
Reserved. Set to zero.
Extend address enable. This bit determines whether the channel uses a 36-bit address bus or a 32-bit address
bus.
0 Channel’s address bus is 32 bits.
1 Channel’s address bus is 36 bits. (Not available in SEC 2.1)
0 Channel done writeback disabled.
1 Channel done writeback enabled.
Upon completion of descriptor processing, if the NT bit is set for global, or if the DN (done notification) bit is set
in the header word of the descriptor, then notify the host by writing back the descriptor header with the
writeback information shown in
descriptor header to determine if that descriptor has been completed.
0 No special action.
1 At the completion of processing each descriptor, write back the status of primary and secondary EUs into
register are not cleared. After the reset sequence is complete, this bit automatically returns to 0 and the
channel resumes normal operation, servicing the next descriptor pointer in the fetch FIFO, if any.
status of primary and secondary EUs into the header dword.
the header dword. In this case, IWSE has no effect.
Table
12-51. This enables the host to poll the memory location of the original
Description
Security Engine (SEC) 2.1
12-93